Verification, Validation and Testing (VVT), is one of the traditional and well established areas of systems engineering. The VVT practitioners manage a stable capability and recognition level. At the same time technological and research advancements create opportunities to leverage the value of the deliverables through the overall system life-cycle. The academic and research deliverables, despite their interest, are poorly diffused in the industrial environment and slowly implemented into VVT tools so that they do not deploy their potentialities. This workshop, proposed by the VVT workgroup of AISE, INAF and Tetra Pak Packaging Solutions proposes the voices of the academic, the research, the VVT SW vendors and the industrial environments about these topics. The systems engineers, the VVT managers and practitioners are invited to share their viewpoints and to collect them during a workshop introduced by an opened round-table drive by qualified and relevant panellists. The workshop’s deliverables shall be distributed to all the participants and refined for further improvements.