Verification Validation and Testing: passion and deployment challenges
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Europe/Rome
CNR Area Ricerca Bologna
CNR Area Ricerca Bologna
Via Gobetti 101 Bologna
Description
Verification, Validation and Testing (VVT), is one of the traditional and well established areas of systems engineering. The VVT practitioners manage a stable capability and recognition level. At the same time technological and research advancements create opportunities to leverage the value of the deliverables through the overall system life-cycle. The academic and research deliverables, despite their interest, are poorly diffused in the industrial environment and slowly implemented into VVT tools so that they do not deploy their potentialities. This workshop, proposed by the VVT workgroup of AISE, INAF and Tetra Pak Packaging Solutions proposes the voices of the academic, the research, the VVT SW vendors and the industrial environments about these topics. The systems engineers, the VVT managers and practitioners are invited to share their viewpoints and to collect them during a workshop introduced by an opened round-table drive by qualified and relevant panellists. The workshop’s deliverables shall be distributed to all the participants and refined for further improvements.
KEY STATEMENT: reinventing the wheel and the anthropological challenge for a physicist to use a standard procedure
Speaker:
Sara Ricciardi(IASFBO)
Slides
09:45
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10:00
INAF Welcome15m
Speaker:
Davide Fierro
10:00
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10:15
Welcome AISE VVT Working Group15m
Speaker:
Carlo Leardi(Tetra Pak)
10:15
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10:30
Ingegneria di Sistema per Macchine Automatiche Complesse15m
KEY STATEMENT: L'ingegneria di Sistema per gestire la complessità del processo di progettazione di macchine e sistemi industriali sempre più performanti e ricchi di fuzionalità: mito o reale opportunità?
Speaker:
Prof.Cesare Fantuzzi(UniMORE)
10:30
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10:45
Modelli di innovazione per creare i prodotti del futuro15m
KEY STATEMENT: in their design process companies have still to understand the potentialities of system-oriented approaches. Test and experimentations are still made too late. Some excellences exist and they can be highlighted as good example to the wider manufacturing and engineering context.
Speaker:
Prof.Sergio Terzi(PoliMI)
10:45
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11:00
VST Project: A case study of the VVT process15m
KEY STATEMENT: Configuration Control during the Integration phase: a key process for VVT
Speaker:
Davide Fierro
11:00
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11:15
Flight hardware test on the two sides of the pond: a researcher perspective.15m
KEY STATEMENT:Test better to test less?
Speaker:
Gianluca Morgante
11:15
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11:45
coffee break
30m
11:45
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12:00
A lean AGILE approach to Service Products Verication and Validation - a case study from a packaging company15m
KEY STATEMENT: I processi Agile possono facilitare l’introduzione di nuove metodologie di V&V dal mondo accademico direttamente nell’industria?
Speakers:
Andrea Margini(Tetra Pak Packaging Solutions), Gaetano Cutrona(Tetrapack)
12:00
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12:15
Multidisciplinary Design Optimization by Simulation15m
KEY STATEMENT:Quale può essere il ruolo della prototipazione virtuale nelle fasi di VVT?
Speaker:
Carlo Poloni(ESTECO)
12:15
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12:30
Agile methodology applicata ad un framework software di sviluppo15m
KEY STATEMENT:Agile methodology applicata ad un framework software di sviluppo
Speaker:
Luca Fioravanti(BLIZZARD)
12:30
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12:45
Cryowaves e' Bologna15m
KEY STATEMENT: key knowledge and expertise for key lab and infrastructures
Speaker:
Fabrizio Villa
12:45
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13:00
Close up15m
Speakers:
Carlo Leardi(Tetra Pak), Sara Ricciardi(IASFBO)
13:00
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13:45
Lunch and Poster session
45m
13:45
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14:05
workshop setup20m
14:05
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15:05
conceptual map analysis and revision1h
we will split in groups to analyze and revise a conceptual map designed by organizer and speakers
Speaker:
Carlo Leardi(TetraPak)
14:25
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15:05
coffe available
40m
15:05
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15:20
Formal Requirements Modeling for Simulation-Based Verification15m
Speaker:
Alfredo Garro(DIMES Universita' della Calabria)
