Verification Validation and Testing: passion and deployment challenges

Thursday 26 May 2016, 09:00 → 20:00 Europe/Rome

CNR Area Ricerca Bologna

Verification, Validation and Testing (VVT), is one of the traditional and well established areas of systems engineering. The VVT practitioners manage a stable capability and recognition level. At the same time technological and research advancements create opportunities to leverage the value of the deliverables through the overall system life-cycle. The academic and research deliverables, despite their interest, are poorly diffused in the industrial environment and slowly implemented into VVT tools so that they do not deploy their potentialities. This workshop, proposed by the VVT workgroup of AISE, INAF and Tetra Pak Packaging Solutions proposes the voices of the academic, the research, the VVT SW vendors and the industrial environments about these topics. The systems engineers, the VVT managers and practitioners are invited to share their viewpoints and to collect them during a workshop introduced by an opened round-table drive by qualified and relevant panellists. The workshop’s deliverables shall be distributed to all the participants and refined for further improvements.

Poster vvi.pdf

09:00 → 09:30 Arrival and registration with welcome coffee¶

09:30 → 09:45 IASF Bo Welcome¶

KEY STATEMENT: reinventing the wheel and the anthropological challenge for a physicist to use a standard procedure

Speaker: Sara Ricciardi (IASFBO)

Slides ricciardi_welcome.pdf

09:45 → 10:00 INAF Welcome¶

Speaker: Davide Fierro

10:00 → 10:15 Welcome AISE VVT Working Group¶

Speaker: Carlo Leardi (Tetra Pak)

10:15 → 10:30 Ingegneria di Sistema per Macchine Automatiche Complesse¶

KEY STATEMENT: L'ingegneria di Sistema per gestire la complessità del processo di progettazione di macchine e sistemi industriali sempre più performanti e ricchi di fuzionalità: mito o reale opportunità?

Speaker: Prof. Cesare Fantuzzi (UniMORE)

10:30 → 10:45 Modelli di innovazione per creare i prodotti del futuro¶

KEY STATEMENT: in their design process companies have still to understand the potentialities of system-oriented approaches. Test and experimentations are still made too late. Some excellences exist and they can be highlighted as good example to the wider manufacturing and engineering context.

Speaker: Prof. Sergio Terzi (PoliMI)

10:45 → 11:00 VST Project: A case study of the VVT process¶

KEY STATEMENT: Configuration Control during the Integration phase: a key process for VVT

Speaker: Davide Fierro

11:00 → 11:15 Flight hardware test on the two sides of the pond: a researcher perspective.¶

KEY STATEMENT:Test better to test less?

Speaker: Gianluca Morgante

11:15 → 11:45 coffee break

11:45 → 12:00 A lean AGILE approach to Service Products Verication and Validation - a case study from a packaging company¶

KEY STATEMENT: I processi Agile possono facilitare l’introduzione di nuove metodologie di V&V dal mondo accademico direttamente nell’industria?

Speakers: Andrea Margini (Tetra Pak Packaging Solutions), Gaetano Cutrona (Tetrapack)

12:00 → 12:15 Multidisciplinary Design Optimization by Simulation¶

KEY STATEMENT:Quale può essere il ruolo della prototipazione virtuale nelle fasi di VVT?

Speaker: Carlo Poloni (ESTECO)

12:15 → 12:30 Agile methodology applicata ad un framework software di sviluppo¶

KEY STATEMENT:Agile methodology applicata ad un framework software di sviluppo

Speaker: Luca Fioravanti (BLIZZARD)

12:30 → 12:45 Cryowaves e' Bologna¶

KEY STATEMENT: key knowledge and expertise for key lab and infrastructures

Speaker: Fabrizio Villa

12:45 → 13:00 Close up¶

Speakers: Carlo Leardi (Tetra Pak), Sara Ricciardi (IASFBO)

13:00 → 13:45 Lunch and Poster session

13:45 → 14:05 workshop setup¶

14:05 → 15:05 conceptual map analysis and revision¶

we will split in groups to analyze and revise a conceptual map designed by organizer and speakers

Speaker: Carlo Leardi (TetraPak)

14:25 → 15:05 coffe available

15:05 → 15:20 Formal Requirements Modeling for Simulation-Based Verification¶

Speaker: Alfredo Garro (DIMES Universita' della Calabria)

15:20 → 15:30 table 1 presentation¶

15:30 → 15:40 table 2 presentation¶

15:40 → 15:50 table 3 presentation¶

15:50 → 16:00 table 4 presentation¶

16:00 → 16:10 table 5 presentation¶

16:10 → 16:20 table 6 presentation¶

16:20 → 16:30 table 7 presentation¶

16:30 → 16:40 closure¶